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advance product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2002 (all rights reserved) cirrus logic, inc. http://www.cirrus.com cs8416 192 khz digital audio interface receiver features complete eiaj cp1201, iec-60958, aes3, s/pdif compatible receiver +3.3 v analog supply(va) +3.3 v to +5.0 v digital interface supply (vl) +3.3 v digital supply (vd) 8:2 s/pdif input mux aes/spdif input pins selectable in hardware mode 3 general purpose outputs (gpo) allow signal routing selectable signal routing to gpo pins s/pdif to tx inputs selectable in hardware mode flexible 3-wire serial digital output port 32 khz to 192 khz sample frequency range low jitter clock recovery pin and microcontroller read access to channel status and user data spi or i 2 c control port software mode and standalone hardware mode differential cable receiver on-chip channel status data buffer memories auto-detection of compressed audio input streams decodes cd q sub-code omck system clock mode general description the cs8416 is a monolithic cmos device which re- ceives and decodes one of 8 channels of audio data according to the iec60958, s/pdif, eiaj cp1201, or aes3 interface standards. the cs8416 has a serial dig- ital audio output port and comprehensive control ability through a selectable control port in software mode or through selectable pins in hardware mode. channel sta- tus data are assembled in buffers, making read access easy. gpo pins may be assigned to route a variety of signals to output pins a low jitter clock recovery mechanism yields a very clean recoveredclockfromtheincomingaes3stream. stand-alone operation allows systems with no microcon- troller to operate the cs8416 with dedicated output pins for channel status data. target applications include a/v receivers, cd-r, dvd receivers, multimedia speakers, digital mixing consoles, effects processors, set-top boxes, and computer and au- tomotive audio systems. ordering information cs8416-cs 28-pin soic -10 to +70c cs8416-cz 28-pin tssop -10 to +70c CS8416-IS 28-pin soic -40 to +85c cs8416-iz 28-pin tssop -40 to +85c clock & data recovery misc. control serial audio output receiver aes3 s/pdif decoder control port & registers rxn rxp1 olrck osclk sdout rst sda/ cdout scl/ cclk ad1/ cdin ad0/ cs va+ agnd filt vl+ dgnd rmck rxp2 rxp3 rxp4 rxp5 rxp6 rxp7 8:2 mux omck gpo0 gpo1 ad2/gpo2 rxp0 vd+ n:3 mux de-emphasis filter c&ubit data buffer aug ?02 ds578pp2
cs8416 2 ds578pp2 table of contents 1 characteristics and specifications ......................................................................... 5 power and thermal characteristics.......................................................................................... 5 absolute maximum ratings ...................................................................................................... 5 digital characteristics ......................................................................................................... ...... 6 switching characteristics - serial audio ports.......................................................................... 7 switching characteristics - control port - spi mode ................................................................ 8 switching characteristics - control port- i 2 c format................................................................. 9 2 typical connection diagrams .................................................................................... 10 3 general description ...................................................................................................... 12 3.1 aes3 and s/pdif sta ndards documents ........................................................................ 12 4 serial audio output port ............................................................................................. 13 4.1 slip/repeat behavior ....................................................................................................... 13 4.2 aes11 behavior .............................................................................................................. 1 4 5 s/pdif receiver ................................................................................................................ .. 16 5.1 8:2 s/pdif input multiplexer ............................................................................................ 16 5.2 pll, jitter attenuation, and clock switching ................................................................... 16 5.2.1 omck system clock mode ................................................................................ 17 5.2.2 pll external components .................................................................................. 17 5.3 error reporting and hold function .................................................................................. 17 5.4 channel status data handling ......................................................................................... 18 5.5 user data handling .......................................................................................................... 18 5.5.1 non-audio auto-detection .................................................................................. 18 6 control port description and timing ..................................................................... 20 6.1 spi mode ..................................................................................................................... .... 20 6.2 i 2 c mode .......................................................................................................................... 21 6.3 general purpose outputs ................................................................................................ 22 6.4 interrupts .................................................................................................................. ........ 22 7 control port register summary ............................................................................. 23 8 control port register bit definitions ................................................................... 25 8.1 control0 (00h)............................................................................................................... .... 25 8.2 control1 (01h)............................................................................................................... .... 25 contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find one nearest you go to important notice "preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "advan ce" product infor- mation describes products that are in development and subject to development changes. cirrus logic, inc. and its subsidiaries ("cirrus") believe th at the infor- mation contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" witho ut warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before placing orders, that in formation being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, inclu ding those pertaining to warranty, patent infringement, and limitation of liability. no responsibility is assumed by cirrus for the use of this information, in cluding use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the prop erty of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the info rmation only for use within your organization with respect to cirrus integrated circuits or other parts of cirrus. this consent does not extend to other copying suc h as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. an export permit needs to be obtained from the competent authorities of the japanese government if any of the products or technologies described in thi sma- terial and controlled under the "foreign exchange and foreign trade law" is to be exported or taken out of japan. an export license and/or quota needs to be obtained from the competent authorities of the chinese government if any of the products or technologies described in this material is subject to the p rc foreign trade law and is to be exported or taken out of the prc. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("critical applications"). cirrus products are not designed, authorized, or warrant- ed to be suitable for use in life-support devices or systems or other critical applications. inclusion of cirrus products in such applications is understood to be fully at the customer's risk. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be tr ade- marks or service marks of their respective owners.
cs8416 ds578pp2 3 8.3 control2 (02h)............................................................................................................... .... 26 8.4 control3 (03h)............................................................................................................... .... 26 8.5 control4 (04h)............................................................................................................... .... 27 8.6 serial audio data format (05h)........................................................................................ 27 8.7 receiver error mask (06h) .............................................................................................. 29 8.8 interrupt mask (07h) ......................................................................................................... 2 9 8.9 interrupt mode msb (08h) and interrupt mode lsb(09h) ................................................ 29 8.10 receiver channel status (0ah) ..................................................................................... 30 8.11 format detect status (0bh)............................................................................................ 30 8.12 receiver error (0ch) ..................................................................................................... 31 8.13 interrupt 1 status (0dh) ................................................................................................. 32 8.14 q-channel subcode (0eh - 17h) .................................................................................... 32 8.15 omck/rmck ratio (18h) .............................................................................................. 33 8.16 channel status registers (19h - 22h) ............................................................................ 33 8.17 iec61937 pc/pd burst preamble (23h - 26h)................................................................ 33 8.18 cs8416 i.d. and version register (7fh)........................................................................ 33 8.19 memory address pointer (map) ..................................................................................... 34 9. pin description - software mode ............................................................................ 35 10 hardware mode .............................................................................................................. 37 10.1 serial audio port formats ............................................................................................. 37 11 pin description - hardware mode ........................................................................... 38 11.1 hardware mode function selection .............................................................................. 40 11.2 hardware mode settings (defaults & controls) ............................................................. 40 12 applications ................................................................................................................. ... 42 12.1 reset, power down and start-up .................................................................................. 42 12.2 id code and revision code .......................................................................................... 42 12.3 power supply, grounding, and pcb layout ................................................................... 42 13 package dimensions ..................................................................................................... 43 14 appendix a: external aes3/spdif/iec60958 receiver components .............. 45 14.1 aes3 receiver external com ponents ........................................................................... 45 14.2 isolating transformer requirements ............................................................................. 45 15 appendix b: channel status buffer management .......................................... 47 15.1 aes3 c hannel status (c) bit management ................................................................... 47 15.2 accessing the e buffer ................................................................................................... 47 15.2.1 serial copy management system (scms) ....................................................... 47
cs8416 4 ds578pp2 list of figures figure 1. audio port master mode timing....................................................................................... 7 figure 2. audio port slave mode and data input timing ................................................................ 7 figure 3. spi mode timing.......................................................................................................... .... 8 figure 4. i2c mode timing.......................................................................................................... .... 9 figure 5. typical connection diagram - software mode............................................................... 10 figure 6. typical connection diagram - hardware mode ............................................................. 11 figure 7. aes3 data format ......................................................................................................... 14 figure 8. serial audio output example formats........................................................................... 15 figure 9. c/u data outputs ......................................................................................................... ... 19 figure 10. de-emphasis filter ..................................................................................................... ... 19 figure 11. control port timing in spi mode ................................................................................. 20 figure 12. control port timing in i 2 c mode .................................................................................. 21 figure 13. hardware mode data flow .......................................................................................... 37 figure 14. professional input circuit ............................................................................................. 4 6 figure 15. transformerless professional input circuit .................................................................. 46 figure 16. consumer input circuit ................................................................................................ 46 figure 17. s/pdif mux input circuit ............................................................................................ 46 figure 18. ttl/cmos input circuit............................................................................................... 46 figure 19. channel status data buffer structure.......................................................................... 47 figure 20. flowchart for reading the e buffer .............................................................................. 47 list of tables table 1. delays by frequency values ................................................................................................. 14 table 2. external pll component values........................................................................................... 17 table 3. gpo pin configurations .................................................................................................... .... 22 table 4. hardware mode serial audio format select ......................................................................... 41
cs8416 ds578pp2 5 1 characteristics and specifications power and thermal characteristics (agnd, dgnd = 0 v, all voltages with respect to ground) notes: 1. assumes that no digital inputs are left floating. it is recommended that all digital inputs be driven high or low at all times. 2. ?-cs? and ?-cz? parts are specified to operate over -10 c to 70 c but are tested at 25 c only. 3. ?-is? and ?-iz? parts are tested over the full -40 c to 85 c temperature range. absolute maximum ratings (agnd, dgnd = 0 v, all voltages with respect to ground) notes: 4. transient currents of up to 100ma will not cause scr latch-up. parameter symbol min typ max unit power supply voltage va+ 3.13 3.3 3.46 v vd+ 3.13 3.3 3.46 v vl+ 3.13 3.3 5.5 v supply current at 48 khz frame rate ia - 5.7 - ma id - 5.9 - ma il - 2.8 - ma supply current at 192 khz frame rate ( note 1 ) ia - 9.4 - ma id - 23 - ma il -7.8-ma supply current in power down ia - 10 - ua id - 70 - ua il - 10 - ua ambient operating temperature: ?-cs? & ?-cz? (note 2) ?-is? & ?-iz? (note 3) t a -10 -40 25 - 70 85 c parameter symbol min max unit power supply voltage vd+, va+, vl+ - 6 volts input current, any pin except supplies ( note 4 ) i in -10 10 ma input voltage v in -0.3 v l +.03 volts ambient operating temperature t a cs8416-c cs8416-i -10 -40 70 85 c c
cs8416 6 ds578pp2 digital characteristics (t a = 25 c for suffixes ?cs? &?cz?, t a = -40 to 85 c for ?is? & ?iz? ; va+ = vd+ = 3.3 v 5%, vl+ = 3.135 v to 5.5 v ) switching characteristics (t a = 25 c for suffixes ?cs? &?cz?, t a = -40 to 85c for ?is? & ?iz? ; va+ = vd+ = 3.3 v 5%, vl+ = 3.135 v to 5.5 v, inputs: logic 0 = 0v, logic 1 = vl+; c l =20pf) parameter symbol min typ max units high-level input voltage except rx n :v ih 2 - (vl+)+0.3 volts low-level input voltage except rx n :v il -0.3 - 0.8 volts low-level output voltage (i o =3.2ma) v ol - - 0.5 volts high-level output voltage (i o =3.2ma) v oh (vl+) - 1 - vl+ volts input hysteresis v h 0.25 - 1.0 volts input leakage current i in -10 - 10 ua differential input sensitivity rxpn to rxn0 - 150 200 mv parameter symbol min typ max units rst/pin low pulse width 200 - - us pll clock recovery sample rate range 30 - 200 khz rmck output jitter (time deviation) - - 200 ps rms rmck output duty-cycle 45 50 55 %
cs8416 ds578pp2 7 switching characteristics - serial audio ports (t a = 25 c for suffixes ?cs? & ?cz?, t a = -40 to 85 c for ?is? & ?iz? ; va+ = vd+ = 3.3 v 5%, vl+ = 3.135 v to 5.5 v, inputs: logic 0 = 0 v, logic 1 = vl+; c l =20pf) notes: 5. in software mode the active edges of osclk are programmable. 6. in software mode the polarity of olrck is programmable. 7. this delay is to prevent the previous osclk edge from being interpreted as the first one after olrck has changed. 8. this setup time ensures that this osclk edge is interpreted as the first one after olrck has changed. parameter symbol min typ max units osclk active edge to sdout output valid (note 5 )t dpd - - 15 ns master mode rmck to osclk active edge delay ( note 5 )t smd 0 - 10 ns rmck to olrck delay ( note 6 )t lmd 0 - 10 ns osclk and olrck duty cycle - 50 - % slave mode osclk period t sckw 36 - - ns osclk input low width t sckl 14 - - ns osclk input high width t sckh 14 - - ns osclk active edge to olrck edge ( notes 5,6,7 )t lrckd 10 - - ns osclk edge setup before osclk active-edge ( notes 5,6,8 )t lrcks 10 - - ns figure 1. audio port master mode timing figure 2. audio port slave mode and data input timing sckh sckl sckw t t t t dpd sdout (input) (input) lrcks t lrckd t osclk olrck osclk olrck (output) (output) rmck t smd t lm d (output)
cs8416 8 ds578pp2 switching characteristics - control port - spi mode (t a = 25 c for suffixes ?cs? &?cz?, t a = -40 to 85c for ?is? & ?iz? ; va+ = vd+ = 3.3 v 5%, vl+ = 3.135 to 5.5v, inputs: logic 0 = 0 v, logic 1 = vl+; c l =20pf) notes: 9. if fs is lower than 46.875 khz, the maximum cclk frequency should be less than 128 fs. this is dictated by the timing requirements necessary to access the channel status memory. access to the control register file can be carried out at the full 6 mhz rate. the minimum allowable input sample rate is 32 khz, so choosing cclk to be less than or equal to 4.1 mhz should be safe for all possible conditions. 10. data must be held for sufficient time to bridge the transition time of cclk. 11. for f sck <1 mhz. parameter symbol min max unit cclk clock frequency ( note 9 )f sck 06.0mhz cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time ( note 10 )t dh 15 - ns cclk falling to cdout stable t pd -50ns rise time of cdout t r1 -25ns fall time of cdout t f1 -25ns rise time of cclk and cdin ( note 11 ) t r2 - 100 ns fall time of cclk and cdin ( note 11 )t r2 - 100 ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t pd cdout t csh figure 3. spi mode timing
cs8416 ds578pp2 9 switching characteristics - control port- i 2 cformat (t a = 25 c; va+ = vd+ = 3.3 v 5%, vl = 3.135 v to 5.5 v inputs: logic 0 = gnd, logic 1 = vl ,c l =20pf) notes: 12. data must be held for sufficient time to bridge the 25 ns transition time of scl. parameter symbol min max unit scl clock frequency f scl - 100 khz bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling ( note 12 )t hdd 10 - ns sda setup time to scl rising t sud 250 - ns rise time of scl and sda t r -25ns fall time scl and sda t f -25ns setup time for stop condition t susp 4.7 - s t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl figure 4. i 2 cmodetiming
cs8416 10 ds578pp2 2 typical connection diagrams cs8416 a seperate analog supply is only necessary in applications where rmck is used for a jitter sensitive tast. for applications where rmck is not used for a jitter sensitive task, connect va+ to vd+ via a ferrite bead. keep decoupling capacitors between va+ and agnd. please see section 5.1 "8:2 s/pdif input multiplexer" and appendix a for typical input configurations and recommended input circuits. * ** filt dgnd agnd ** *** for best jitter performance connect the filter ground directly to the agnd pin. seetable2forpllfiltervalues. *** rxn rxp0 rxp1 rxp2 rxp3 aes3 / s/pdif sources microcontroller scl / cclk sda / cdout omck clock source rst ad1 / cdin gpo0 rmck clock control serial audio input device olrck osclk sdout external interface rxp4 rxp5 rxp6 rxp7 ad0 / cs gpo1 ad2/gpo2 rflt cflt crip 47k ? 10 f +3.3v to +5v 0.1 f 1nf +3.3v ferrite bead +3.3v analog supply * va+ vd+ vl+ * 10 f 0.1 f 1nf 0.1 f 1nf vl+ vl+ figure 5. typical connection diagram - software mode
cs8416 ds578pp2 11 10 f cs8416 0.1 f 1nf +3.3v a seperate analog supply is only necessary in applications where rmck is used for a jitter sensitive tast. for applications where rmck is not used for a jitter sensitive task, connect va+ to vd+ via a ferrite bead. keep decoupling capacitors between va+ and agnd. please see section 5.1 "8:2 s/pdif input multiplexer" and appendix a for typical input configurations and recommended input circuits. *** filt dgnd agnd rflt cflt crip *** **** for best jitter performance connect the filter ground directly to the agnd pin. see table 2 for pll filter values. **** rxn rxp0 rxp1 rxp2 rxp3 aes3 / s/pdif sources hardware control rxsel1 txsel0 txsel1 nv/rerr 96khz rcbl u c ferrite bead +3.3v analog supply ** omck clock source rxsel0 rst audio va+ vd+ vl+ tx rmck clock control serial audio input device olrck osclk sdout external interface 47k ? these pins must be pulled high to vl+ or low to dgnd through a 47k ? resistor. * ** ** * * * * * * 10 f 0.1 f 1nf 0.1 f 1nf +3.3v to +5v vl+ vl+ figure 6. typical connection diagram - hardware mode
cs8416 12 ds578pp2 3 general description the cs8416 is a monolithic cmos device which receives and decodes audio data according to the aes3, iec60958, s/pdif, and eiaj cp1201 inter- face standards. the cs8416 utilizes an 8:2 multiplexer to select between eight inputs for decoding and to allow an input signal to be routed to an output of the cs8416. input data is either differential or single- ended. a low jitter clock is recovered from the in- coming data using a pll. the decoded audio data is output through a configurable, 3-wire output port. the channel status and q-channel subcode portion of the user data are assembled in registers and may be accessed through an spi or i 2 c port. three general purpose output (gpo) pins are pro- vided to allow a variety of signals to be accessed under software control. in hardware mode, dedicat- ed pins are used to select audio stream inputs for decoding and transmission to a dedicated tx pin. hardware mode also allows direct access to chan- nel status and user data output pins. figure 5 and figure 6 show the power supply and external connections to the cs8416 when config- ured for software and hardware modes. please note that all i/o pins, including rxn and rxp[7:0], op- erate at the vl+ voltage. 3.1 aes3 and s/pdif standards documents this document assumes that the user is familiar with the aes3 and s/pdif data formats. it is advis- able to have current copies of the aes3, iec60958, and iec61937 specifications on hand for easy ref- erence. the latest aes3 standard is available from the au- dio engineering society or ansi at www.aes.org or at www.ansi.org . obtain a copy of the latest iec60958/61937 standard from ansi or from the international electrotechnical commission at www.iec.ch . the latest eiaj cp-1201 standard is available from the japanese electronics bureau. application note 22: overview of digital audio in- terface data structures contains a useful tutorial on digital audio specifications, but it should not be considered a substitute for the standards. the paper an understanding and implementation of the scms serial copy management system for digital audio transmission , by clifton sanchez, is an excellent tutorial on scms. it is available from the aes as reprint 3518.
cs8416 ds578pp2 13 4 serial audio output port a 3-wire serial audio output port is provided. the port can be adjusted to suit the attached device set- ting the control registers. the following parameters are adjustable: master or slave, serial clock fre- quency, audio data resolution, left or right justifica- tion of the data relative to left/right clock, optional one-bit cell delay of the first data bit, the polarity of the bit clock, and the polarity of the left/right clock. by setting the appropriate control bits, many for- mats are possible. figure 8 shows a selection of common output for- mats, along with the control bit settings. a special aes3 direct output format is included, which al- lows the serial output port access to the v, u, and c bits embedded in the serial audio data stream. the p bit, which would normally be a parity bit, is replaced by a z bit, which is used to indicate the start of each block. the received channel status block start signal is also available as the rcbl pin in hardware mode and through a gpo pin in soft- ware mode. in master mode, the left/right clock (olrck) and the serial bit clock (osclk) are outputs, derived from the recovered rmck clock. in slave mode, olrck and osclk are inputs. olrck is nor- mally synchronous to the appropriate master clock, but osclk can be asynchronous and discontinu- ous if required. by appropriate phasing of olrck and control of the serial clocks, multiple cs8416?s can share one serial port. olrck should be con- tinuous, but the duty cycle can be less than the specified typical value of 50% if enough serial clocks are present in each phase to clock all the data bits. when in slave mode, the serial audio output port cannot be set for right-justified data. the cs8416 allows immediate mute of the serial audio output port audio data by the mutesao bit of control register 1. 4.1 slip/repeat behavior when using the serial audio output port in slave mode with an olrck input that is asynchronous to the incoming aes3 data, the interrupt bit oslip (bit 5 in the interrupt 1 status register, 0dh) is pro- vided to indicate when repeated or dropped sam- ples occur. refer to figure 7 for a aes3 data format diagram. when the serial output port is configured as slave, depending on the relative frequency of olrck to the input aes3 data (z/x) preamble frequency, the data will be slipped or repeated at the output of the cs8416. after a fixed delay from the z/x preamble (a few periods of the internal clock, which is running at 256fs), the circuit will look back in time until the previous z/x preamble: 1) if during that time, the internal data buffer was not updated, then a slip has occurred. data from the previous frame will be output and oslip will be set to 1. due to the oslip bit being ?sticky,? it will remain 1 until the register is read. it will then be reset until another slip/re- peat condition occurs. 2) if during that time the internal data buffer did not update between two positive or negative edges (depending on olrpol) of olrck, then a repeat has occurred. in this case the buff- er data was updated twice, so the part has lost one frame of data. this event will also trigger oslip to be set to 1. due to the oslip bit be- ing ?sticky,? it will remain 1 until the register is read. it will then be reset until another slip/re- peat condition occurs. 3) if during that time, it did see a positive edge on olrck (or negative edge if the solrpol is set to 1) then no slip or repeat has happened. due to the oslip bit being ?sticky,? it will re- main in its previous state until either the regis- ter is read or a slip/repeat condition occurs.
cs8416 14 ds578pp2 if the user reads oslip as soon as the event trig- gers, over a long period of time the rate of occur- ring int will be equal to the difference in frequency between the input aes data and the slave serial output lrck. the cs8416 uses a hys- teresis window when a slip/repeat event occurs. the slip/repeat is triggered when an edge of ol- rck passes a window size from the beginning of the z/x preamble. without the hysteresis window, jitter on olrck with a frequency very close to fs could slip back and forth, causing multiple slip/re- peat events. the cs8416 uses a hysteresis window to ensure that only one slip/repeat happens even with jitter on olrck. 4.2 aes11 behavior when olrck is configured as a master, the posi- tive or negative edge of olrck (depending on the setting of solrpol in register 05h) will be within -1.0%(1/fs) to 1.1%(1/fs) from the start of the pre- amble x/z. in master mode, the latency through the part is dependent on the input sample frequency. the delay through the part from the beginning of the preamble to the active edge of olrck for the various sample frequencies is given in table 1 .in master mode without the de-emphasis filter en- gaged, the latency of the audio data will be 3 frames. when olrck is configured as a slave any syn- chronized input within +/-28%(1/fs) from the pos- itive or negative edge of olrck (depending on the setting of solrpol in register 05h) will be treated as being sampled at the same time. since the cs8416 has no control of the olrck in slave mode, the latency of the data through the part will be a multiple of 1/fs plus the delay between ol- rck and the preambles. both of these conditions are within the tolerance range set forth in the aes11 standard. x channel a data y channel b data z y x y channel a data channel b data channel a data channel b data frame 191 frame 0 frame 1 preambles olrck (in slave mode) figure 7. aes3 data format fs (khz) delay (ns) 32 96.6 44.1 78.6 48 74.6 64 60.6 96 50.6 192 tbd table 1. delays by frequency values
cs8416 ds578pp2 15 msb lsb left right msb is (out) olrck osclk sdout olrck osclk sdout 2 left justified (out) msb lsb olrck osclk sdout msb lsb msb left right aes3 direct (out) vz uc lsb lsb vz uc right justified (out) olrck osclk sdout msb lsb msb lsb msb left right msb lsb left right lsb msb lsb msb extended msb extended msb ex figure 8. serial audio output example formats x = don?t care to match format, but does need to be set to the desired setting * see serial output data format register bit descriptions for an explanation of the meaning of each bit soms* sosf* sores[1:0]* sojust* sodel* sospol* solrpol* left justified x x xx 0 0 0 0 i 2 s xxxx0101 right justified 1 x xx 1 0 0 0 aes3 direct x x 11 0 0 0 0
cs8416 16 ds578pp2 5 s/pdif receiver the cs8416 includes an aes3/spdif digital au- dio receiver. the aes3 receiver accepts and de- codes audio and digital data according to the aes3, iec60958 (s/pdif), and eiaj cp-1201 interface standards. the receiver consists of an analog differ- ential input stage, driven through analog input pins rxp0 to rxp7 and a common rxn, a pll based clock recovery circuit, and a decoder which sepa- rates the audio data from the channel status and user data. software mode the first 5 bytes of both channels status block is stored in dedicated registers. channel a status data is stored in control port registers 19h to 1dh. chan- nel b status data is stored in control port registers 1eh to 22h. q subcode data is stored in control port registers 0eh to 17h. pc burst preamble is stored in control port regis- ters 23h and 24h. pd burst preamble is stored in control port registers 25h and 26h. u and c data may be selected for output on gpo pins. external components are used to terminate and iso- late the incoming data cables from the cs8416. these components are detailed in appendix a. hardware mode u and c bits are output on pins 18 and 19 respec- tively. see section ?hardware mode function se- lection? on page 40 and ?hardware mode settings (defaults & controls)? on page 40 to configure these pins. 5.1 8:2 s/pdif input multiplexer the cs8416 employs a 8:2 s/pdif input multi- plexer to accommodate up to eight channels of in- put digital audio data. digital audio data may be single- ended or differential. differential inputs uti- lize rxp[0-7] and a shared rxn. single ended sig- nals are accommodated by using rxp inputs and ac coupling rxn to ground. all inputs to the cs8416 8:2 input multiplexer should be coupled through a capacitor. the recom- mended capacitor value is 0.01uf to 0.1uf. the recommended dielectrics are cog or x7r. software mode the multiplexer select line control is accessed through bits rxsel[2:0] in control port register 4. the multiplexer defaults to rxp0. the second output of the input multiplexer is used to provide the selected input as a source to be out- put on a gpo pin via the internal tx pin. this pass through signal is selected by txsel[2:0] in con- trol port register 04h. the single-ended signal is re- solved to full-rail, but is not de-jittered before it is output. hardware mode in hardware mode the input to the decoder is select- ed by dedicated pins, rxsel[1:0]. the pass through signal is selected by dedicated pins, txsel[1:0] for output on the dedicated tx pin. selectable inputs are restricted to rxp0 to rxp3 for both the receiver and the tx output pin. these inputs are selected by rxsel[1:0] and tx- sel[1:0] respectively. general unused multiplexer inputs should be left floating or grounded. the input voltage range for the input multiplexer is set by the i/o power supply pin, vl+. the input voltage of the rxp and rxn pins is also set by the level of vl+. 5.2 pll, jitter attenuation, and clock switching an on-chip phase locked loop (pll) is used to re- cover the clock from the incoming data stream.
cs8416 ds578pp2 17 there are some applications where low jitter in the recovered clock, presented on the rmck pin, is important. for this reason, the pll has been de- signed to have good jitter attenuation characteris- tics. in addition, the pll has been designed to only use the preambles of the aes3 or s/pdif stream to provide lock update information to the pll. this results in the pll being immune to data dependent jitter affects because the aes3 or s/pdif pream- bles do not vary with the data. in applications where jitter must be minimized, special attention should be given to reducing the noise on the analog power supply and ground for the pll filter components. connecting the filter components directly to agnd will help decrease jitter. the pll has the ability to lock onto a wide range of input sample rates with no external component changes. 5.2.1 omck system clock mode a special clock switching mode is available that al- lows the omck clock input to replace rmck when the pll becomes unlocked. in software mode this feature is enabled by setting swclk bit in control1 register to a ?1?. in hardware mode this feature is always active. clock switching is accomplished without spurious transitions or glitches on rmck. osclk and olrck are derived from the omck input when the clock has been switched and the se- rial port is in master mode. when the pll loses lock, the frequency of the vco drops to ~500 khz. when this system clock mode is not enabled, the osclk and olrck will be based on the vco when the pll is not locked 5.2.2 pll external components the pll behavior is affected by the external filter component values. figure 5 and figure 6 show the recommended configuration of the two capacitors and one resistor required. there are two sets of component values recommended, depending on the sample rate of the application. (see table 2 .) the default set, called ?fast?, accommodates input sam- ple rates of 96 khz to 192 hz with no component changes. it has the highest corner frequency jitter attenuation curve, and takes the shortest time to lock. the alternate component set, called ?medi- um? allows the lowest input sample rate to be 32 khz, and increases the lock time of the pll. lock times are worst case for an fs transition from un- locked state to locking to 192 khz. it is important to treat the pll flt pin as a low level analog input. it is suggested that the ground end of the pll filter be returned directly to the agnd pin independently of the digital ground plane. 5.3 error reporting and hold function software mode while decoding the incoming aes3 data stream, the cs8416 can identify several kinds of error, in- dicated in the receiver error register (0ch). the errors indicated are: 1) qcrc ? crc error in q subcode data 2) ccrc ? crc error in channel status data 3) unlock ? pll is not locked to incoming data stream 4) v ? data validity bit is set 5) conf ? input data stream is near error condi- tion due to jitter degradation 6) bip ? biphase encoding error 7) par ? parity error in incoming data range (khz) rflt cflt crip settling time 32 - 192 1 k ? 220 nf 10 nf 11ms medium 96 - 192 3 k ? 22 nf 1 nf 4ms fast table 2. external pll component values
cs8416 18 ds578pp2 the error bits are ?sticky?; they are set on the first occurrence of the associated error and will remain set until the user reads the register through the con- trol port. this enables the register to log all un- masked errors that occurred since the last time the register was read. as a result of the bits ?stickiness?, it is necessary to perform two reads on these registers to see if the er- ror condition still exists. the receiver error mask register (06h) allows masking of individual errors. the bits in this regis- ter default to 00h and serve as masks for the corre- sponding bits of the receiver error register. if a mask bit is set to 1, the error is unmasked, which implies the following: its occurrence will be report- ed in the receiver error register, induce a pulse on rerr, invoke the occurrence of a rerr interrupt, and affect the current audio sample according to the status of the hold bits. the exceptions are the qcrc and ccrc errors, which do not affect the current audio sample, even if unmasked. the hold bits allow a choice of: holding the previous sample replacing the current sample with zero (mute) or not changing the current audio sample rerr ? the logical or of all unmasked receiver error bits, not ?sticky?. rerr may be selected for output on a gpo pin. nverr ? non-validity receiver error hardware mode in hardware mode the user may choose between nverr or rerr by pulling the nv/rerr pin low or high respectively. 5.4 channel status data handling software mode the first 5 bytes of the channel status block are de- coded into the receiver channel status registers 19h - 22h. registers 19h - 1dh contain the a chan- nel status data. registers 1eh - 22h contain the b channel status data. the emph , c, and u bits may be selected on gpo pins by appropriately setting the gpoxsel bits in control port registers 02h and 03h. the encoded channel status bits which indicate sample word length are decoded according to aes3-1992 or iec 60958. the number of auxiliary bits are reported in bits 7 to 4 of the receiver chan- nel status register. appendix b describes the overall handling of channel status and user data. 5.5 user data handling received user data may also be output to the u pin under the control of a control register bit. vlrck (a virtual word clock, available through gpo pins, that can used to frame the c/u output) and olrck in serial port master mode can be made available to qualify the u data output in software mode. figure 9 illustrates the timing. in hardware mode, only olrck in master mode is available to qualify the u output. if the incoming user data bits have been encoded as q- channel subcode, the data is de- coded, buffered, and presented in 10 consecutive register locations. an interrupt may be enabled to indicate the decoding of a new q-channel block, which may be read through the control port. 5.5.1 non-audio auto-detection an aes3 data stream may be used to convey non- audio data, thus it is important to know whether the incoming aes3 data stream is digital audio or not. this information is typically conveyed in channel status bit 1 (audio ), which is extracted automati- cally by the cs8416. however, certain non-audio sources, such as ac-3 or mpeg encoders, may not adhere to this convention, and the bit may not be properly set. the cs8416 aes3 receiver can detect such non-audio data through the use of an autode- tect module. the autodetect module is similar to
cs8416 ds578pp2 19 autodetect software used in cirrus logic dsps. if the aes3 stream contains sync codes in the proper format for iec61937 or dts data transmission, an internal autodetect signal will be asserted. if the sync codes no longer appear after a certain amount of time, autodetection will time-out and autodetect will be de-asserted until another format is detected. in hardware mode, the audio pin is the logical or of autodetect and the re- ceived channel status bit 1. in software mode the audio pin is available through the gpo pins. al- so, the specific data or audio format found by the autodetect module is available in register 0bh. ad- ditionally, the pc/pd burst preambles are available in registers 23h-26h. if non-audio data is detected, the data is still processed exactly as if it were nor- mal audio. the exception is the use of de-emphasis auto-select feature which will bypass the de-em- phasis filter if the input stream is detected to be non-audio. it is up to the user to mute the outputs as required. rcbl out vlrck c, u output rcbl goes high 2 frames after receipt of a z pre-amble, and is high for 16 frames. vlrck is a virtual word clock, available through gpo pins, that can used to frame the c/u ouput. vlrck duty cycle is 50%. vlrck frequency is always equal to the incoming frame rate. if the serial audio output port is in master mode, vlrck = olrck. c, u transitions are aligned within 1% of vlrck period to vlrck edges figure 9. c/u data outputs figure 10. de-emphasis filter f2 f1 -10 3.183 frequency, khz t1 = 50us 0 10.61 gain, db t2 =15us
cs8416 20 ds578pp2 6 control port description and timing the control port is used to access the registers, al- lowing the cs8416 to be configured for the desired operational modes and formats. in addition, chan- nel status and user data may be read through the control port. the operation of the control port may be completely asynchronous with respect to the au- dio sample rates. however, to avoid potential inter- ference problems, the control port pins should remain static if no operation is required. the control port has 2 modes: spi and i 2 c, with the cs8416 acting as a slave device in both modes. spi mode is selected if there is a high to low transition on the ad0/cs pin, after the rst pin has been brought high. i 2 c mode is selected by connecting the ad0/cs pin to vl+ or dgnd, thereby perma- nently selecting the desired ad0 bit address state. 6.1 spi mode in spi mode, cs is the cs8416 chip select signal, cclk is the control port bit clock (input into the cs8416 from the microcontroller), cdin is the in- put data line from the microcontroller, cdout is the output data line to the microcontroller. data is clocked in on the rising edge of cclk and out on the falling edge. figure 11 shows the operation of the control port in spi mode. to write to a register, bring cs low. the first seven bits on cdin form the chip address and must be 0010000. the eighth bit is a read/write in- dicator (r/w ), which should be low to write. the next eight bits form the memory address pointer (map), which is set to the address of the register that is to be updated. the next eight bits are the data which will be placed into the register designated by the map. during writes, the cdout output stays in the hi-z state. it may be externally pulled high or low with a 47 k ? resistor, if desired. there is a map auto increment capability, enabled by the incr bit in the map register. if incr is a zero, the map will stay constant for successive read or writes. if incr is set to a 1, the map will auto increment after each byte is read or written, al- lowing block reads or writes of successive regis- ters. in the autoincrement mode, the map is incremented in a linear fashion. allowance must be made for unused registers. to read a register, the map has to be set to the cor- rect address by executing a partial write cycle which finishes (cs high) immediately after the map byte. the map auto increment bit (incr) may be set or not, as desired. to begin a read, bring cs low, send out the chip address and set the map msb lsb data byte 1 byte n r/w r/w address chip address chip cdin cclk cs cdout msb lsb msb lsb 0010000 0010000 map = memory address pointer, 8 bits, msb first high impedance figure 11. control port timing in spi mode
cs8416 ds578pp2 21 read/write bit (r/w ) high. the next falling edge of cclk will clock out the msb of the addressed register (cdout will leave the high impedance state). if the map auto increment bit is set to 1, the data for successive registers will appear consecu- tively. the auto increment function is strictly linear. this may result in operations on undefined registers. reads from undefined registers will produce inde- terminate results. writing to undefined registers will be ignored. 6.2 i 2 c mode in i 2 c mode, sda is a bidirectional data line. data is clocked into and out of the part by the clock, scl, with the clock to data relationship as shown in figure 12 . there is no cs pin. each individual cs8416 is given a unique address. pins ad0 and ad1 form the two least significant bits of the chip address and should be connected to vl+ or dgnd as desired. the gpo2 pin is used to set the ad2 bit by connecting a 47k resistor from the gpo2 pin to vl+ or to dgnd. the state of the pin is sensed while the cs8416 is being reset. the upper 4 bits of the 7-bit address field are fixed at 0010. to com- municate with a cs8416, the chip address field, which is the first byte sent to the cs8416, should match 0010 followed by the settings of the gpo2, ad1, and ad0. the eighth bit of the address is the r/w bit. if the operation is a write, the next byte is the memory address pointer (map) which selects the register to be read or written. if the operation is a read, the contents of the register pointed to by the map will be output. setting the auto increment bit in map allows successive reads or writes of con- secutive registers. each byte is separated by an ac- knowledge bit. the ack bit is output from the cs8416 after each input byte is read, and is input to the cs8416 from the microcontroller after each transmitted byte. sda scl 0010 ad2-0 r/w start ack data7-0 ack data7-0 ack stop note 2 note 1 note 3 figure 12. control port timing in i 2 cmode notes: 1. ad2 is derived from a resistor attached to the gpo2 pin. ad1 and ad0 are determined by the state of the corresponding pins. 2. if operation is a write, this byte contains the memory address pointer, map. 3. if operation is a read, the last bit of the read should be nack (high).
cs8416 22 ds578pp2 6.3 general purpose outputs three general purpose outputs are provided to allow the equipment designer flexibility in configuring the cs8416. fourteen signals are available to be routed to the gpos. gpo pins may be configured to provide the following data: notes: 13. frequency = 25 mhz max, duty cycle not guaranteed, target duty cycle = 50% @ f s =48khz. 6.4 interrupts the cs8416 has a comprehensive interrupt capa- bility. the int pin may be set to be active low, ac- tive high or active low with no active pull-up transistor. this last mode is used for active low, wired-or hook- ups, with multiple peripherals connected to the microcontroller interrupt input pin. many conditions can cause an interrupt, as listed in the interrupt status register descriptions. each source may be masked off through mask register bits. in addition, each source may be set to rising edge, falling edge, or level sensitive. combined with the option of level sensitive or edge sensitive modes within the microcontroller, many different configurations are possible, depending on the needs of the equipment designer. function code definition tx 0000 aes/spdif input selected by txsel[2:0] emph 0001 state of emph bit in incoming stream. same polarity as emphb bit. int 0010 cs8416 interrupt c 0011 channel status bit u 0100 user data bit rerr 0101 receiver error nverr 0110 non-validity receiver error rcbl 0111 receiver channel status block 96khz 1000 input f s 88.1 audio 1001 non-audio indicator for decoded input stream vlrck 1010 virtual lrck gnd 1011 fixed low level vdd 1100 vdd fixed high level hrmck 1101 f s x 512 ( note 13 ) codes 1110 to 1111 - reserved table 3. gpo pin configurations
cs8416 ds578pp2 23 7 control port register summary addr (hex) r/w function 7 6 5 4 3 2 1 0 00 r/w control 0 0 0 0 0 0 trunc reserved reserved 01 r/w control1 swclk mutsao int1 int0 hold1 hold0 rmckf chs 02 r/w control2 detci emph_c ntl2 emph_c ntl1 emph_c ntl0 gpo0se l3 gpo0se l2 gpo0se l1 gpo0se l0 03 r/w control3 gpo1se l3 gpo1se l2 gpo1se l1 gpo1se l0 gpo2se l3 gpo2se l2 gpo2se l1 gpo2se l0 04 r/w control4 run rxd rxsel2 rxsel1 rxsel0 txsel2 txsel1 txsel0 05 r/w serial audio data format soms sosf sores1 sores0 sojust sodel sospol solr- pol 06 r/w receiver error mask 0 qcrcm ccrcm unlock m vm confm bipm parm 07 r/w interrupt mask 0 pcchm oslipm detcm cchm rerrm qchm fchm 08 r/w interrupt mode msb 0 pcch1 oslip1 detc1 cch1 rerr1 qch1 fch1 09 r/w interrupt mode lsb 0 pcch0 oslip0 detc0 cch0 rerr0 qch0 fch0 0a r receiver channel status aux3 aux2 aux1 aux0 pro copy orig emph 0b r audio format detect 0 pcm iec61937 dts_ld dts_cd reserved dgtl_si l 96khz 0c r receiver error 0 qcrc ccrc unlock v conf bip par 0d r interrupt status 0 pcch oslip detc cch rerr qch fch 0e r q-channel subcode [0:7] con- trol con- trol con- trol con- trol addres s addres s addres s addres s 0f r [8:15] track track track track track track track track 10 r [16:23] index index index index index index index index 11 r [24:31] minute minute minute minute minute minute minute minute 12 r [32:39] second second second second second second second second 13 r [40:47] frame frame frame frame frame frame frame frame 14 r [48:55] zero zero zero zero zero zero zero zero 15 r [56:63] abs minute abs minute abs minute abs minute abs minute abs minute abs minute abs minute 16 r [64:71] abs sec- ond abs sec- ond abs sec- ond abs sec- ond abs sec- ond abs sec- ond abs sec- ond abs sec- ond 17 r [72:79] abs frame abs frame abs frame abs frame abs frame abs frame abs frame abs frame 18 r omck_rmck ratio orr7 orr6 orr5 orr4 orr3 orr2 orr1 orr0 19 r channel a status ac0[7] ac0[6] ac0[5] ac0[4] ac0[3] ac0[2] ac0[1] ac0[0] 1a r channel a status ac1[7] ac1[6] ac1[5] ac1[4] ac1[3] ac1[2] ac1[1] ac1[0] 1b r channel a status ac2[7] ac2[6] ac2[5] ac2[4] ac2[3] ac2[2] ac2[1] ac2[0] 1c r channel a status ac3[7] ac3[6] ac3[5] ac3[4] ac3[3] ac3[2] ac3[1] ac3[0] 1d r channel a status ac4[7] ac4[6] ac4[5] ac4[4] ac4[3] ac4[2] ac4[1] ac4[0] 1e r channel b status bc0[7] bc0[6] bc0[5] bc0[4] bc0[3] bc0[2] bc0[1] bc0[0] 1f r channel b status bc1[7] bc1[6] bc1[5] bc1[4] bc1[3] bc1[2] bc1[1] bc1[0] 20 r channel b status bc2[7] bc2[6] bc2[5] bc2[4] bc2[3] bc2[2] bc2[1] bc2[0] 21 r channel b status bc3[7] bc3[6] bc3[5] bc3[4] bc3[3] bc3[2] bc3[1] bc3[0] 22 r channel b status bc4[7] bc4[6] bc4[5] bc4[4] bc4[3] bc4[2] bc4[1] bc4[0] 23 r burst preamble pc byte 0 pc0[7] pc0[6] pc0[5] pc0[4] pc0[3] pc0[2] pc0[1] pc0[0]
cs8416 24 ds578pp2 24 r burst preamble pc byte 1 pc1[7] pc1[6] pc1[5] pc1[4] pc1[3] pc1[2] pc1[1] pc1[0] 25 r burst preamble pd byte 0 pd0[7] pd0[6] pd0[5] pd0[4] pd0[3] pd0[2] pd0[1] pd0[0] 26 r burst preamble pd byte 1 pd1[7] pd1[6] pd1[5] pd1[4] pd1[3] pd1[2] pd1[1] pd1[0] 7f r id & version id3 id2 id1 id0 ver3 ver2 ver1 ver0 addr (hex) r/w function 7 6 5 4 3 2 1 0
cs8416 ds578pp2 25 8 control port register bit definitions 8.1 control0 (00h) trunc ? determines if the audio word length is set according to the incoming channel status data as decoded by the aux[3:0] bits. the resulting word length in bits is 24-aux[3:0]. default = 0 0 ? incoming data is not truncated 1 ? incoming data is truncated according to the length specified in the channel status data truncation occurs before the de-emphasis filter. trunc has no effect on output data if de-emphasis filter is not used. reserved [1:0] ? these bits may change state depending on the input audio data. 8.2 control1 (01h) swclk - lets omck determine rmck, osclk, olrck when pll loses lock default = ?0? 0 ? output clocks determined by pll 1 ? output clocks determined by omck rmckf ? recovered master clock frequency default = ?0? 0 ? frequency is 256 fs 1 ? frequency is 128 fs mutesao - mute control for the serial audio output port default = ?0? 0-sdout(notmuted) 1 ? sdout (muted) hold[1:0] ? determine how received audio sample is affected when a receive error occurs default = ?00? 00 ? hold last audio sample 01 ? replace the current audio sample with 00 (mute) 10- do not change the received audio sample 11 - reserved 76543210 0 0 0 0 0 trunc reserved reserved 76543210 swclk mutesao int1 int0 hold1 hold0 rmckf chs
cs8416 26 ds578pp2 int[1:0] - interrupt output pin (int) control default = ?00? 00 - active high; high output indicates interrupt condition has occurred 01 - active low, low output indicates an interrupt condition has occurred 10 - open drain, active low. requires an external pull-up resistor on the int pin. thus it is not recom- mended to multiplex int onto gpo2 in i 2 c control port mode since an external resistor is re- quired on gpo2 to specify the ad2 bit of the chip address. 11 ? reserved chs ? sets which channel's c data is decoded in the receiver channel status register 0 ? a channel 1 ? b channel 8.3 control2 (02h) detci ? d to e status transfer inhibit default = ?0? 0 ? allow update 1 ? inhibit update emph_cntl[2:0] ? de-emphasis filter control default = 000 000 ? de-emphasis filter off 001 ? 32 khz setting 010 ? 44.1 khz setting 011 ? 48 khz 100 ? 50us/15us de-emphasis filter auto-select on. coefficients(32, 44.1 or 48 khz or no de-empha- sis filter at all) match the pre-emphasis and sample frequency indicators in the channel status bits of channel a. thus it is impossible to have de-emphasis applied to one channel but not the other. also it turns off the de-emphasis filter if the audio data is detected to be non-linear data. gpo0sel[3:0] ? gpo0 source select. see gpo section in main text for settings table. default = 0000 8.4 control3 (03h) 76543210 detci emph_cntl2 emph_cntl1 emph_cntl0 gpo0sel3 gpo0sel2 gpo0sel1 gpo0sel0 7 6 543210 gpo1sel3 gpo1sel2 gpo1sel1 gpo1sel0 gpo2sel3 gpo2sel2 gpo2sel1 gpo2sel0
cs8416 ds578pp2 27 gpo1sel[3:0] ? gpo1 source select default = 0000 gpo2sel[3:0] ? gpo2 source select default = 0000 8.5 control4 (04h) run - controls the internal clocks, allowing the cs8416 to be placed in a ?powered down?, low current consumption, state. default = ?0? 0 - internal clocks are stopped. internal state machines are reset. the fully static control port is oper- ational, allowing registers to be read or changed. power consumption is low. 1 - normal part operation. this bit must be written to the 1 state to allow the cs8416 to begin opera- tion. all input clocks should be stable in frequency and phase when run is set to 1. rxd ? rmck high-z default = ?0? 0 -rmck is an output, clock is derived from input frame rate 1 ? rmck becomes high impedance rx_sel[2:0] ? selects rxp0 to rxp7 for input to the receiver default =000 000 ? rxp0 001 ? rxp1, etc tx_sel[2:0] ? selects rxp0 to rxp7 as the input for gpo tx source default =000 000 ? rxp0 001 ? rxp1, etc 8.6 serial audio data format (05h) soms - master/slave mode selector default = ?0? 76543210 run rxd rxsel2 rxsel1 rxsel0 txsel2 txsel1 txsel0 76543210 soms sosf sores1 sores0 sojust sodel sospol solrpol
cs8416 28 ds578pp2 0 - serial audio output port is in slave mode 1 - serial audio output port is in master mode sosf - osclk frequency (for master mode) default = ?0? 0-64*fs 1 - 128*fs sores[1:0] - resolution of the output data on sdout default = ?00? 00 - 24-bit resolution 01 - 20-bit resolution 10 - 16-bit resolution 11 - direct copy of the received nrz data from the aes3 receiver including c, u, and v bits. the time slot occupied by the z bit is used to indicate the location of the block start. this setting forces the sojust bit to be ?0?. sojust - justification of sdout data relative to olrck default = ?0? 0 - left-justified 1 - right-justified (master mode only and sores 11) sodel - delay of sdout data relative to olrck, for left-justified data formats (this control is only valid in left justified mode) default = ?0? 0 - msb of sdout data occurs in the first osclk period after the olrck edge 1 - msb of sdout data occurs in the second osclk period after the olrck edge sospol - osclk clock polarity default = ?0? 0 - sdout sampled on rising edges of osclk 1 - sdout sampled on falling edges of osclk solrpol - olrck clock polarity default = ?0? 0 - sdout data is for the left channel when olrck is high 1 - sdout data is for the right channel when olrck is high
cs8416 ds578pp2 29 8.7 receiver error mask (06h) the bits in this register serve as masks for the corresponding bits of the receiver error register. if a mask bit is set to 1, the error is unmasked, meaning that its occurrence will appear in the receiver error register, will affect the rerr pin, will affect the rerr interrupt, and will affect the current audio sample according to the status of the hold bit. if a mask bit is set to 0, the error is masked, meaning that its occurrence will not appear in the receiver error register, will not affect the rerr pin, will not affect the rerr interrupt, and will not affect the current audio sample. the ccrc and qcrc bits behave differently from the other bits: they do not affect the current audio sample even when un- masked. this register defaults to 00h. 8.8 interrupt mask (07h) the bits of this register serve as a mask for the interrupt status register .ifamaskbitissetto1,the error is unmasked, meaning that its occurrence will affect the int pin and the status register. if a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the internal int signal or the status register. the bit positions align with the corresponding bits in interrupt status register . this register defaults to 00h. the int signal may be selected to appear on the gpo pins. 8.9 interrupt mode msb (08h) and interrupt mode lsb(09h) the two interrupt mode registers form a 2-bit code for each interrupt status register function. there are three ways to set the int pin active in accordance with the interrupt condition. in the rising edge active mode, the int pin becomes active on the arrival of the interrupt condition. in the falling edge active mode, the int pin becomes active on the removal of the interrupt condition. in level active mode, the int interrupt pin becomes active during the interrupt condition. be aware that the active level(active high or low) only depends on the int[1:0] bits. these registers default to 00h. 00 - rising edge active 01 - falling edge active 10 - level active 11 - reserved 76543210 0 qcrcm ccrcm unlockm vm confm bipm parm 76543210 0 pcchm oslipm detcm cchm rerrm qchm fchm 76543210 0 pcch1 oslip1 detc1 cch1 rerr1 qch1 fch1 0 pcch0 oslip0 detc0 cch0 rerr0 qch0 fch0
cs8416 30 ds578pp2 8.10 receiver channel status (0ah) the bits in this register can be associated with either channel a or b of the received data. the desired channel is selected with the chs bit of the control1 register. aux3:0 - incoming auxiliary data field width, as indicated by the incoming channel status bits, de- coded according to iec60958 and aes3. 0000 - auxiliary data is not present 0001 - auxiliary data is 1 bit long 0010 - auxiliary data is 2 bits long 0011 - auxiliary data is 3 bits long 0100 - auxiliary data is 4 bits long 0101 - auxiliary data is 5 bits long 0110 - auxiliary data is 6 bits long 0111 - auxiliary data is 7 bits long 1000 - auxiliary data is 8 bits long 1001 - 1111 reserved pro - channel status block format indicator 0 - received channel status block is in consumer format 1 - received channel status block is in professional format copy - scms copyright indicator 0 - copyright asserted 1 - copyright not asserted if the category code is set to general in the incoming aes3 stream, copy- right will always be indicated by copy, even when the stream indicates no copyright. orig - scms generation indicator, decoded from the category code and the l bit. 0 - received data is 1st generation or higher 1 - received data is original note: copy and orig will both be set to 1 if incoming data is flagged as professional or if the receiver is not in use. emph ? indicates whether the input audio data has been pre-emphasized. also indicates turning on of the de-emphasis filter during de-emphasis auto-select mode. 0 ? 50us/15us pre-emphasis indicated 1 ? 50us/15us pre-emphasis not indicated 8.11 format detect status (0bh) note: pcm, dts_ld, dts_cd and iec61937 are mutually exclusive. pcm ? uncompressed pcm data was detected iec61937 ? iec61937 data was detected dts_ld ? dts_ld data was detected 76543210 aux3 aux2 aux1 aux0 pro copy orig emph 76543210 0 pcm iec61937 dts_ld dts_cd reserved dgtl_sil 96khz
cs8416 ds578pp2 31 dts_cd ? dts_cd data was detected reserved ? this bit may change state depending on the input audio data. dgtl_sil ? digital silence was detected: at least 2047 consecutive constant samples of the same 24-bit audio data on both channels. 96khz ? if input sample rate is 48 khz, outputs a ?0?. outputs a ?1? if the sample rate is 88.1 khz. otherwise output indeterminate. 8.12 receiver error (0ch) this register contains the aes3 receiver and pll status bits. unmasked bits will go high on occur- rence of the error, and will stay high until the register is read. reading the register resets all bits to 0, unless the error source is still true. bits that are masked off in the receiver error mask register will always be 0 in this register. qcrc - q-subcode data crc error indicator. updated on q-subcode block boundaries 0 - no error 1 - error ccrc - channel status block cyclic redundancy check bit. updated on cs block boundaries, valid in pro mode 0 - no error 1 - error unlock - pll lock status bit. updated on cs block boundaries. 0-plllocked 1 - pll out of lock v - received aes3 validity bit status. updated on sub-frame boundaries. 0 - data is valid and is normally linear coded pcm audio 1 - data is invalid, or may be valid compressed audio conf - confidence bit. updated on sub-frame boundaries. 0 - no error 1 - confidence error. this indicates that the received data eye opening is less than half a bit period, indicating a poor link that is not meeting specifications. bip - bi-phase error bit. updated on sub-frame boundaries. 0 - no error 1 - bi-phase error. this indicates an error in the received bi-phase coding. par - parity bit. updated on sub-frame boundaries. 0 - no error 1 - parity error 76543210 0 qcrc ccrc unlock v conf bip par
cs8416 32 ds578pp2 8.13 interrupt 1 status (0dh) for all bits in this register, a ?1? means the associated interrupt condition has occurred at least once since the register was last read. a ?0? means the associated interrupt condition has not occurred since the last reading of the register. reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true. status bits that are masked off in the associated mask register will always be ?0? in this register. pcch ? pc burst preamble change. indicates that the pc byte has changed from its previous value. the user has tbd frames to read new value before it can potentially be overwritten again. if the iec61937 bit in the format detect sta- tus register goes high, it will cause a pcch interrupt even if the pc byte hasn?t changed since the last time the iec61937 bit went high. oslip - serial audio output port data slip interrupt when the serial audio output port is in slave mode, and olrck is asynchronous to the port data source, this bit will go high every time a data sample is dropped or repeated. detc - d to e c-buffer transfer interrupt. the source for this bit is true during the d to e buffer transfer in the c bit buffer management process. c_change -indicates that the current 10 bytes of channel status is different from the previous 10 bytes. (5 bytes per channel) rerr - a receiver error has occurred. the receiver error register may be read to determine the nature of the error which caused the inter- rupt. qch ? a new block of q-subcode is available for reading. the data must be read within 588 aes3 frames after the interrupt occurs to avoid corruption of the data by the next block. fch ? format change: goes high when the pcm, iec61937, dts_ld, dts_cd, or dgtl_sil bits in the format detect status register transition from 0 to 1. when these bits in the format detect status register transition from 1 to 0, an interrupt will not be generated. 8.14 q-channel subcode (0eh - 17h) each byte is lsb first with respect to the 80 q-subcode bits q[79:0]. thus bit 7 of address 0eh is q[0] while bit 0 of address 0eh is q[7]. similarly bit 0 of address 17h corresponds to q[79]. 76543210 0 pcch oslip detc cch rerr qch fch 76543210 control control control control address address address address track track track track track track track track index index index index index index index index minute minute minute minute minute minute minute minute second second second second second second second second frame frame frame frame frame frame frame frame zero zero zero zero zero zero zero zero abs minute abs minute abs minute abs minute abs minute abs minute abs minute abs minute abs second abs second abs second abs second abs second abs second abs second abs second abs frame abs frame abs frame abs frame abs frame abs frame abs frame abs frame
cs8416 ds578pp2 33 8.15 omck/rmck ratio (18h) this register allows the calculation of the incoming sample rate by the host microcontroller from the equation orr=fso/fsi. the fso is determined by omck, whose frequency is assumed to be 256 fso. orr is represented as an unsigned 2-bit integer and a 6-bit fractional part. the value is mean- ingful only after the pll has reached lock. for example, if the omck is 12.288mhz, fso would be 48khz (48khz = 12.288mhz/256). then if the input sample rate is also 48khz, you would get 1.0 from the orr register.(the value from the orr register is hexadecimal, so the actual value you will get is 40h). if f so /f si > 3 63 / 64 , orr will saturate at the value ffh. also, there is no hysteresis on orr. therefore a small amount of jitter on either clock can cause the lsb orr[0] to oscillate. orr[7:6] - integer part of the ratio (integer value=integer(srr[7:6])) orr[5:0] - fractional part of the ratio (fraction value=integer(srr[5:0])/64) 8.16 channel status registers (19h - 22h) 8.17 iec61937 pc/pd burst preamble (23h - 26h) 8.18 cs8416 i.d. and version register (7fh) id[3:0]= 0010 ver[3:0] = 0001 (revision a) 76543210 orr7 orr6 orr5 orr4 orr3 orr2 orr1 orr0 25 channel a status byte 0 ac0[7] ac0[6] ac0[5] ac0[4] ac0[3] ac0[2] ac0[1] ac0[0] 26 channel a status byte 1 ac1[7] ac1[6] ac1[5] ac1[4] ac1[3] ac1[2] ac1[1] ac1[0] 27 channel a status byte 2 ac2[7] ac2[6] ac2[5] ac2[4] ac2[3] ac2[2] ac2[1] ac2[0] 28 channel a status byte 3 ac3[7] ac3[6] ac3[5] ac3[4] ac3[3] ac3[2] ac3[1] ac3[0] 29 channel a status byte 4 ac4[7] ac4[6] ac4[5] ac4[4] ac4[3] ac4[2] ac4[1] ac4[0] 30 channel b status byte 0 bc0[7] bc0[6] bc0[5] bc0[4] bc0[3] bc0[2] bc0[1] bc0[0] 31 channel b status byte 1 bc1[7] bc1[6] bc1[5] bc1[4] bc1[3] bc1[2] bc1[1] bc1[0] 32 channel b status byte 2 bc2[7] bc2[6] bc2[5] bc2[4] bc2[3] bc2[2] bc2[1] bc2[0] 33 channel b status byte 3 bc3[7] bc3[6] bc3[5] bc3[4] bc3[3] bc3[2] bc3[1] bc3[0] 34 channel b status byte 4 bc4[7] bc4[6] bc4[5] bc4[4] bc4[3] bc4[2] bc4[1] bc4[0] 35 burst preamble pc byte 0 pc0[7] pc0[6] pc0[5] pc0[4] pc0[3] pc0[2] pc0[1] pc0[0] 36 burst preamble pc byte 1 pc1[7] pc1[6] pc1[5] pc0[4] pc1[3] pc1[2] pc1[1] pc1[0] 37 burst preamble pd byte 0 pd0[7] pd0[6] pd0[5] pc0[4] pd0[3] pd0[2] pd0[1] pd0[0] 38 burst preamble pd byte 1 pd1[7] pd1[6] pd1[5] pd1[4] pd1[3] pd1[2] pd1[1] pd1[0] 76543210 id3 id2 id1 id0 ver3 ver2 ver1 ver0
cs8416 34 ds578pp2 8.19 memory address pointer (map) incr - auto increment address control bit default = ?0? 0 - disabled 1-enabled map6:map0 - register address 76 543210 incr map6 map5 map4 map3 map2 map1 map0
cs8416 ds578pp2 35 9. pin description - software mode 1 2 3 4 5 6 7 821 22 23 24 25 26 27 28 9 10 11 12 17 18 19 20 13 14 15 16 rxp3 rxp2 rxp1 rxp0 rxn va+ agnd filt rst rxp4 rxp5 rxp6 rxp7 ad0/cs olrck osclk sdout omck rmck vd+ dgnd vl+ gpo0 gpo1 ad2/gpo2 sda/cdout scl/cclk ad1/cdin rxp[7:0] rxn 13 12 11 10 1 2 3 4 5 additional aes3/spdif receiver port ( input ) - single-ended receiver inputs carrying aes3 or s/pdif digital data. these inputs comprise the 8:2 s/pdif input multiplexer. the select line control is accessed using the control 4 register. please note that any unused inputs can be left floating or tied to ground. see appendix a for recommended input circuits. aes/spdif input - used along with rxp[x] to form an aes3 differential input. in single-ended operation this should be capacitively coupled to ground. va+ vd+ vl+ 6 23 21 positive analog power - positive supply for the analog section. nominally +3.3 v. this supply should be as quiet as possible since noise on this pin will directly affect the jitter performance of the recovered clock positive digital power ? nominally 3.3 v positive ? interface power ? 3.3 v to 5.0 v: this supply sets the cs8416 i/o levels, including rxpx & rxn agnd dgnd 6 22 analog ground - ground for the analog circuitry in the chip. agnd and dgnd should be con nected to a common ground area under the chip. digital & i/o ground filt 8 pll loop filter ( output ) - an rc network should be connected between this pin and analog ground. for minimum pll jitter, return the ground end of the filter network directly to agnd
cs8416 36 ds578pp2 rst 9 reset ( input )-whenrst is low, the cs8416 enters a low power mode and all internal states are reset. on initial power up, rst must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. ad0/cs 14 address bit 0 (i 2 c) / control port chip select (spi) ( input) - a falling edge on this pin puts the cs8416 into spi control port mode. with no falling edge, the cs8416 defaults to i 2 c mode. in i 2 c mode, ad0 is a chip address pin. in spi mode, cs is used to enable the control port interface on the cs8416 ad1/cdin 15 address bit 1 (i 2 c)/serialcontroldatain(spi) ( input )-ini 2 c mode, ad1 is a chip address pin. in spi mode, cdin is the input data line for the control port interface scl/cclk 16 control port clock ( input ) - serial control interface clock and is used to clock control data bits into and out of the cs8416. sda/ cdout 17 serial control data i/o (i 2 c) / data out (spi) ( input/output )-ini 2 c mode, sda is the control i/o data line. sda is open drain and requires an external pull-up resistor to vl+. in spi mode, cdout is the output data from the control port interface on the cs8416 ad2/gpo2 18 general purpose output 2 (output) -ifusingthei 2 c control port, this pin must be pulled high or low througha47k ? resistor. see ?general purpose outputs? on page 22 for gpo functions. gpo1 19 general purpose output 1 (output) see ?general purpose outputs? on page 22 for gpo functions. gpo0 20 general purpose output 0 (output) see ?general purpose outputs? on page 22 for gpo functions. sdout 26 serial audio output data ( output ) - audio data serial output pin. this pin must be pulled high to vl+ througha47k ? resistor to place the part in software mode. olrck 28 serial audio output left/right clock ( input / output ) - word rate clock for the audio data on the sdout pin. frequency will be the output sample rate (fs) osclk 27 serial audio output bit clock ( input / output ) - serial bit clock for audio data on the sdout pin omck 25 system clock ( input ) - when the omck system clock mode is enabled using the swclk bit in the control 1 register, the clock signal input on this pin is output through rmck. omck serves as reference signal for omck/rmck ratio expressed in register 24 rmck 24 input section recovered master clock ( output ) - input section recovered master clock output when pll is used. frequency defaults to 256x the sample rate (fs) and may be set to 128x. it may also be tri-stated by the rxd bit in the control 4 register (04h).
cs8416 ds578pp2 37 10 hardware mode the cs8416 has a hardware mode which allows using the device without a microcontroller. hardware mode is selected by connecting the 47k pull-up/down resistor on the sdout pin to ground. various pins change function in hardware mode, described in the hardware mode pin definition section (section 11). hardware mode data flow is shown in figure 13 . audio data is input through the aes3/spdif receiver, and routed to the serial audio output port. the decoded c and u bits are also output, clocked at both edges of olrck (master mode only, see figure 9 ). an error in the incoming audio stream will be indicated on the nv/rerr. this pin can be configured in one of two ways. if rerr is chosen by pulling nv/rerr to ground, the previous audio sample is held and passed to the serial audio output port if the validity bit is high, or a parity, bi-phase, confidence or pll lock error occurs during the current sample. if nverr is chosen by pulling nv/rerr to vl+, only par- ity, bi-phase, confidence or pll lock error cause the previous audio sample to be held. 10.1 serial audio port formats in hardware mode, only a limited number of alternative serial audio port formats are available. table 4 de- fines the equivalent software mode bit settings for each format. the start-up options, shown in table 4 , allow choice of the serial audio output port as a master or slave, and the serial audio port format. nv/rerr power supply pins (va+, vd+, vl+, agnd, dgnd, the reset pin (rst) and the pll filter pin (filt) are omitted from the diagram. please refer to the typical connection diagram for connection details. rxp1 4:2 mux rxp2 rxp3 rxp0 96khz rmck rxsel[1:0] txsel[1:0] audio rcbl rxn aes3 rx & decoder omck tx olrck osclk sdout c u de-emphasis filter serial audio output figure 13. hardware mode data flow
cs8416 38 ds578pp2 11 pin description - hardware mode 1 2 3 4 5 6 7 821 22 23 24 25 26 27 28 9 10 11 12 17 18 19 20 13 14 15 16 rxp3 rxp2 rxp1 rxp0 rxn va+ agnd filt rst rxsel1 rxsel0 txsel1 txsel0 nv/rerr olrck osclk sdout omck rmck vd+ dgnd vl+ tx c u rcbl 96 khz audio rxp[3:0] rxn 1 2 3 4 5 additional aes3/spdif receiver port ( input ) - single-ended receiver inputs carrying aes3 or s/pdif digital data. these inputs comprise the 4:2 s/pdif input multiplexer. the select line control is the rxsel[1:0] pins. please note that any unused inputs can be left floating. see appendix a for rec- ommended input circuits. aes/spdif input - used along with rxp[x] to form an aes3 differential input. in single-ended operation this should be capacitively coupled to ground . vd+ va+ vl+ 23 6 21 positive digital power ?3.3v positive analog power ? 3.3 v positive interface power ? 3.3v ?5.0v dgnd agnd 22 7 digital/interface ground analog ground rx_sel0 rx_sel1 10 11 receiver_mux selector (input) - used to select which pin, rxp[3:0], is used for the receiver input. tx_sel0 tx_sel1 12 13 tx pin mux selection (input) - used to select which pin, rxp[3:0], is used for the tx pin output. filt 8 pll filter pin ? a rc network should be connected from this pin to agnd. for best pll jitter performance, this pin should be returned directly to the agnd pin rst 9 reset (input) ? active low input . resets cs8416 to default state, configuration pins are read on the rising edge of this pin nv/rerr 14 non-validity receiver error/receiver error (output)
cs8416 ds578pp2 39 audio 15 audio channel status bit (output) ? when low, a valid linear pcm audio stream is indicated. 96khz 16 96 khz sample rate detect (output) - if input sample rate is 48 khz, ouputs a ?0?. outputs a ?1? if thesamplerateis 88.1 khz. otherwise output indeterminate. rcbl 17 receiver channel status block ( output ) - indicates the beginning of a received channel status block. rcbl goes high two frames after the reception of a z preamble, remains high for 16 frames and then returns low for the remainder of the block. rcbl changes on rising edges of rmck. u 18 user data ( output ) - outputs user data from the aes3 receiver, clocked by the rising and falling edges of olrck. c 19 channel status data ( output ) - outputs channel status data from the aes3 receiver, clocked by the ris ing and falling edges of olrck. tx 20 s/pdif mux pass through ( output) sdout 26 serial audio output data ( output ) - audio data serial output pin. this pin must be pulled to low to dgnd through a 47 k ? resistor. olrck 28 serial audio output left/right clock ( input / output ) - word rate clock for the audio data on the sdout pin. frequency will be the output sample rate (fs). osclk 27 serial audio output bit clock ( input / output ) - serial bit clock for audio data on the sdout pin. omck 25 system clock ( input ) - when the omck system clock mode is enabled using the swclk bit in the control 1 register, the clock signal input on this pin is output through rmck. omck serves as reference signal for omck/rmck ratio expressed in register 24 rmck 24 recovered master clock ( output ) - recovered master clock output when pll is locked to the incoming aes3 stream. frequency is 128/256x the sample rate (fs).
cs8416 40 ds578pp2 11.1 hardware mode function selection hardware mode and several options for that mode are selected by pulling cs8416 pins up or down imme- diately after rst is released. 1) sdout ? hardware/software mode select 2) rcbl ? serial port slave/master select 3) nv/rerr ? nverr/rerr select 4) audio ? serial port format select[1] (0/1) 5) c ? serial port format select[0] (0/1) 6) u ? rmck frequency select (256/128) 7) 96khz ? emphasis audio match off/on for these pins, the first option is selected by using a pulldown. the second option is selected via a pullup. 11.2 hardware mode settings (defaults & controls) control register 0 trunc = 0 fs[1:0] = 00 control register 1 swclk = 1 mutsao = 0 int = n/a, there is no interrupt pin in hardware mode hold[1:0] = 00 rmckf = set by u pin pull-up/down at startup chs = 0 control register 2 detci = n/a emph_cntl[2] = set by 96khz pull-up/down at startup emph_cntl[1:0] = 00 gpo0sel[3:0] = n/a control register 3 gpo1sel[3:0] = n/a gpo2sel[3:0] = n/a control register 4 run = 1 rxd = 0 rx_sel[2] = 0 rx_sel[1:0] = rx_sel[1:0] pins
cs8416 ds578pp2 41 tx_sel[2] = 0 tx_sel[1:0] = tx_sel[1:0] pins control register 5 - serial port format sosm: set by rcbl pullup/pulldown at startup. bits[6:0]: set by startup pull up/pull down on audio & c at startup: control register 6 ? receiver error mask {qcrcm,crcm} = 00 {unlockm,confm,bipm,parm} = 1111 vm set by pullup/pulldown on nv/rerr select control register 7 - interrupt status mask n/a control register 8,9 - interrupt mode n/a serial port format select [1:0] sosf sores[1:0] sojust sodel sospol solrpol 00 (left justified) 0 00 0 0 0 0 01(i2s 24 bit) 0 00 0 1 0 1 10 (right justified) 0 00 1 0 0 0 11 (direct aes3) 0 11 0 0 0 0 table4.hardwaremodeserialaudioformatselect
cs8416 42 ds578pp2 12 applications 12.1 reset, power down and start-up when rst is low, the cs8416 enters a low power mode and all internal states are reset, including the control port and registers, and the outputs are mut- ed. in software mode, when rst is high, the con- trol port becomes operational and the desired settings should be loaded into the control registers. writing a 1 to the run bit will then cause the part to leave the low power state and begin operation. after the pll has settled, the serial audio outputs will be enabled. some options within the cs8416 are controlled by a start-up mechanism. during the reset state, some of the pins are reconfigured internally to be inputs. immediately upon exiting the reset state, the level of these pins is sensed. the pins are then switched to be outputs. this mechanism allows output pins to be used to set alternative modes in the cs8416 by connecting a 47k resistor to between the pin and either vl+ (hi) or dgnd (lo). for each mode, every start-up option select pin must have an ex- ternal pull-up or pull-down resistor. in software mode, the only start-up option pins are gpo2, which are used to set a chip address bit for the con- trol port in i 2 c mode, and sdout, which selects between hardware and software modes. the hard- ware mode uses many start-up options, which are detailed in the hardware definition section at the end of this data sheet. 12.2 id code and revision code the cs8416 has a register that contains a 4-bit code to indicate that the addressed device is a cs8416. this is useful when other cs84xx family members are resident in the same system, allowing common software modules. the cs8416 4-bit revision code is also available. this allows the software driver for the cs8416 to identify which revision of the device is in a particular system, and modify its behavior accordingly. to allow for future revisions, it is strongly recommend that the revision code is read into a variable area within the microcontroller, and used wherever appropriate as revision details become known. 12.3 power supply, grounding, and pcb layout for most applications, the cs8416 can be operated from a single +3.3 v supply, following normal supply decoupling practices. (see figure 5 and figure 6 ). for applications where the recovered input clock, output on the rmck pin, is required to be low jitter, then use a separate, quiet, analog +3.3 v supply for va+, decoupled to agnd. in addition, a separate region of analog ground plane around the filt, agnd, va+, rxp0-7 and rxn pins is recommended. vl+ sets the level for the digital inputs and outputs, as well as the aes/spdif inputs. extensive use of power and ground planes, ground plane fill in unused areas and surface mount decou- pling capacitors are recommended. decoupling ca- pacitors should be mounted on the same side of the board as the cs8416 to minimize inductance ef- fects, and all decoupling capacitors should be as close to the cs8416 as possible. refer to an159 for examples of proper techniques.
cs8416 ds578pp2 43 13 package dimensions inches millimeters dim min nom max min nom max a 0.093 0.098 0.104 2.35 2.50 2.65 a1 0.004 0.008 0.012 0.10 0.20 0.30 b 0.013 0.017 0.020 0.33 0.42 0.51 c 0.009 0.011 0.013 0.23 0.28 0.32 d 0.697 0.705 0.713 17.70 17.90 18.10 e 0.291 0.295 0.299 7.40 7.50 7.60 e 0.040 0.050 0.060 1.02 1.27 1.52 h 0.394 0.407 0.419 10.00 10.34 10.65 l 0.016 0.026 0.050 0.40 0.65 1.27 0 4 8 0 4 8 jedec #: ms-013 controlling dimension is millimeters 28l soic (300 mil body) package drawing d h e b a1 a c l seating plane 1 e
cs8416 44 ds578pp2 notes: 1. ?d? and ?e1? are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension ?b? does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximum material condition. dambar intrusion shall not reduce dimension ?b? by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a----0.47----1.20 a1 0.002 0.004 0.006 0.05 0.10 0.15 a2 0.03150 0.035 0.04 0.80 0.90 1.00 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 d 0.378 bsc 0.382 bsc 0.386 bsc 9.60 bsc 9.70 bsc 9.80 bsc 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- 0.026 bsc -- -- 0.65 bsc -- l 0.020 0.024 0.029 0.50 0.60 0.75 0 4 8 0 4 8 jedec #: mo-153 controlling dimension is millimeters. 28l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
cs8416 ds578pp2 45 14 appendix a: external aes3/spdif/iec60958 receiver components 14.1 aes3 receiver external components the cs8416 aes3 receiver is designed to accept both the professional and consumer interfaces. the digital audio specifications for professional use call for a balanced receiver, using xlr connectors, with 110 ? 20% impedance. the xlr connector on the receiver should have female pins with a male shell. since the receiver has a very high input im- pedance, a 110 ? resistor should be placed across the receiver terminals to match the line impedance, as shown in figure 14 and figure 15 . although transformers are not required by the aes, they are, however, strongly recommended. if some isolation is desired without the use of trans- formers, a 0.01 f capacitor should be placed in se- ries with each input pin (rxp0 and rxn0) as shown in figure . however, if a transformer is not used, high frequency energy could be coupled into the receiver, causing degradation in analog perfor- mance. figure 14 and figure 15 show an optional dc blocking capacitor (0.1 fto0.47 f) in series with the cable input. this improves the robustness of the receiver, preventing the saturation of the trans- former, or any dc current flow, if a dc voltage is present on the cable. in the configuration of systems, it is important to avoid ground loops and dc current flowing down the shield of the cable that could result when boxes with different ground potentials are connected. generally, it is good practice to ground the shield to the chassis of the transmitting unit, and connect the shield through a capacitor to chassis ground at the receiver. however, in some cases it is advanta- geous to have the ground of two boxes held to the same potential, and the cable shield might be de- pended upon to make that electrical connection. generally, it may be a good idea to provide the op- tion of grounding or capacitively coupling the shield to the chassis. in the case of the consumer interface, the standards call for an unbalanced circuit having a receiver im- pedance of 75 ? 5%. the connector for the con- sumer interface is an rca phono socket. the receiver circuit for the consumer interface is shown in figure . figure shows an implementation of the input s/pdif multiplexer using the consumer in- terface. the circuit shown in figure maybeusedwhenex- ternal rs422 receivers, optical receivers or other ttl/cmos logic outputs drive the cs8416 receiv- er section. 14.2 isolating transformer requirements please refer to the application note an134: aes and spdif recommended transformers for re- sources on transformer selection.
cs8416 46 ds578pp2 1 xlr twisted pair 110 ? 110 ? cs8416 rxp0 rxn0 *seetext 1 xlr twisted pair 110 ? 11 0 ? cs841 6 rxp0 rxn0 0.01 f 0.01 f *seetext figure 14. professional input circuit figure 15. transformerless professional input circuit rxp7 rxn0 rxp0 rxp6 75 ? .01 f .01 f .01 f . . . .01 f 75 ? coax 75 ? 75 ? 75 ? coax 75 ? coax cs8416 figure 16. consumer input circuit figure 17. s/pdif mux input circuit rca phono rxp0 rxn0 cs8416 coax 75 ? 75 ? 0.01 f 0.01 f rxp0 rxn0 cs8416 0.01 f 0.01 f ttl/cmos gate figure 18. ttl/cmos input circuit
cs8416 ds578pp2 47 15 appendix b: channel status buffer management 15.1 aes3 channel status (c) bit management the cs8416 contains sufficient ram to store the first 5 bytes of c data for both a and b channels (5 x 2 x 8 = 80 bits). the user may read from this buffer ? s ram through the control port. the buffering scheme involves 2 80-bit buffers, named d and e, as shown in figure 19 . the msb of each byte represents the first bit in the serial c data stream. for example, the msb of byte 0 (which is at control port address 32) is the consum- er/professional bit for channel status block a. the first buffer (d) accepts incoming c data from the aes receiver. the 2nd buffer (e) accepts entire blocks of data from the d buffer. the e buffer is also accessible from the control port, allowing reading of the c data. 15.2 accessing the e buffer the user can monitor the incoming data by reading the e buffer, which is mapped into the register space of the cs8416, through the control port. the user can configure the interrupt enable register to cause interrupts to occur whenever d to e buffer transfers occur. this allows determination of the al- lowable time periods to interact with the e buffer. also provided is a d to e inhibit bit. this may be used whenever ? long ? control port interactions are occurring. a flowchart for reading the e buffer is shown in figure 20 . since a d to e interrupt just occurred af- ter reading, there is a substantial time interval until the next d to e transfer (approximately 192 frames worth of time). this is usually plenty of time to ac- cess the e data without having to inhibit the next transfer. 15.2.1 serial copy management system (scms) in software mode, the cs8416 allows read access to all the channel status bits. for consumer mode scms compliance, the host microcontroller needs to read and interpret the category code, copy bit and l bit appropriately. in hardware mode, the scms protocol can be fol- lowedbyeitherusingthecopyandorigoutput pins, or by using the c bit serial output pin. these options are documented in the hardware mode sec- tion of this data sheet. control port from aes3 receiver e 24 words 8-bits 8-bits ab d received data buffer figure 19. channel status data buffer structure d to e interrupt occurs optionally set d to e inhibit read e data if set, clear d to e inhibit return figure 20. flowchart for reading the e buffer

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